This paper addresses the implementation of model predictive control
  (MPC) at millisecond range, or faster, sampling rates.  This is
  achieved by designing a custom integrated circuit architecture that
  is specifically targeted to the MPC problem.  As opposed to the more
  usual approach using a generic serial architecture processor, the
  design here is implemented using a field programmable gate array
  (FPGA) and employs parallelism, pipelining and specialized numerical
  formats. The performance of this approach is profiled via the
  control of a 14th order resonant structure with 12 sample prediction
  horizon at 200us sampling rate. The results indicate that no
  more than 30us are required to compute the control action.  A
  feasibility study indicates that the design can also be implemented
  in 130nm CMOS technology, with a core area of 2.5mm<sup>2</sup>.  These
  results illustrate the feasibility of MPC for reasonably complex
  systems, using relatively cheap, small, and low-power computing
  hardware.