This paper considers the system architecture and design issues for implementation of on-line Model Predictive Control (MPC) in Field Programmable Gate Arrays (FPGAs) and Application Specific Integrated Circuits (ASICs). In particular, the computationally itensive tasks of fast matrix QR factorisation, and subsequent sequential quadratic programming, are addressed for control law computation. An important aspect of this work is the study of appropriate data word-lengths for various essential stages of the overall solution strategy.